1625-1675the information provided herein is believed to be reliable at press time. sirenza microdevices assumes no responsibili ty for inaccuracies or omissions. sirenza microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user?s own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. sirenza microde vices does not authorize or warrant any sirenza microdevices product for use in life-support devices and/or systems. copyright 2003 s irenza microdevices, inc. all worldwide rights reserved. 303 s. technology court, phone: (800) smi-mmic http://ww w.sirenza.com broomfield, co 80021 1 eds-102936 rev e sirenza mi crodevices? xd010-14s-d4f 15w power module is a robust 2- stage class a/ab amplifier module for use in gsm and edge rf applica- tions. this module is optimized to minimize the evm at typical operating levels. the power transistors are fabr icated using sirenz a's latest, high performance ldmos process. this unit operates from a single voltage supply and has internal temperature compensation of the bias voltage to ensure stable performance over the full temperature range. it is a drop-in, no-tune solution for medium power appl ications requiring high efficiency, excellent linearity, and unit-to-unit repeatabi lity. it is internally matched to 50 ohms. key specifications symbol parameter unit min. typ. max. frequency frequency of operation mhz 925 960 p 1db output power at 1db compression (single tone) w 10 15 gain gain at 12w output power (cw) db 30 32 35 gain flatness peak-to-peak gain variation db 0.4 1.0 irl input return loss 12w cw db 12 18 efficiency drain efficiency at 12w cw % 27 31 linearity rms evm at 8w edge output % 2.5 peak evm at 8w edge output % 6.7 3 rd order imd at 12w pep (two tone) dbc -35 -30 delay signal delay from pin 1 to pin 4 ns 2.5 phase linearity deviation from lin ear phase (peak-to-peak) deg 0.5 r th, j-l thermal resistance stage 1 (junction-to-case) oc/w 11 r th, j-2 thermal resistance stage 2 (junction-to-case) oc/w 4 xd010-14s-d4f 925-960 mhz class a/ab 15w power amplifier module product features applications ? 50 w rf impedance ? 15w output p 1db ? single supply operation : nominally 28v ? high gain: 32 db at 942 mhz ? high efficiency: 31% at 942 mhz ? robust 8000v esd (hbm), class 3b ? high peak power for lower ber ? ultra-low evm ? base station pa driver ? repeater ? gsm / edge product description bias network temperature compensation v d2 d1 v rf out rf in stage 2 stage 1 1 23 4 case flange = ground test conditions z in = z out = 50 ? , v dd = 28.0v, i dq1 = 230 ma, i dq2 =158 ma, t flange = 25oc functional block diagram
xd010-14s-d4f 925-960 mhz 15w power amp module 303 s. technology court phone: (800) smi-mmic http://www.sirenza.com broomfield, co 80021 2 eds-102936 rev e pin description pin # function description 1 rf input module rf input. this pin is internally connected to dc ground. do not apply dc voltages to the rf leads. care must be taken to protect against video transients that may damage the active devices. 2v d1 this is the drain voltage for t he first stage. nominally +28vdc 3v d2 this is the drain voltage for the 2 nd stage of the amplifier module. the 2 nd stage gate bias is temperature compensated to maintain constant quiscent drain current over the operating temperature range. see note 1. 4rf output module rf output. this pin is internally connected to dc gr ound. do not apply dc voltages to the rf leads. care must be taken to protect against video transients that may damage the active devices. flange gnd exposed area on the bottom side of the package needs to be me chanically attached to the ground plane of the board for optimum thermal and rf performance. see mounting inst ructions in application note an-060 on sirenza?s web site. simplified device schematic absolute maximum ratings parameters value unit 1 st stage bias voltage (v d1 )35v 2 nd stage bias voltage (v d2 )35v rf input power +20 dbm load impedance for continuous operation with- out damage 5:1 vswr output device channel temperature +200 oc operating temperature range -20 to +90 oc storage temperature range -40 to +100 oc operation of this device beyond any one of these limits may cause per- manent damage. for reliable continuous operation see typical setup val- ues specified in the table on page one. caution: esd sensitive appropriate precaution in handling, packaging and testing devices must be observed. note 1: the internally generated gate voltage is thermally compen- sated to maintain constant quiescent current over the temper- ature range listed in the data sheet. no compensation is provided for gain changes with te mperature. this can only be accomplished with agc external to the module. note 2: internal rf decoupling is incl uded on all bias leads. no addi- tional bypass elements are requi red, however some applica- tions may require energy storage on the drain leads to accommodate time-varying waveforms. note 3: this module was designed to have its leads hand soldered to an adjacent pcb. the maximum soldering iron tip temperature should not exceed 700 c, and the soldering iron tip should not be in direct contac t with the lead for longer than 10 seconds. refer to app note an060 (www.sirenza.com) for further installation instructions. temperature compensation bias network v d2 d1 v rf 1 q1 q2 2 3 4 case flange = ground in out rf quality specifications parameter unit typical esd rating human body model, jedec document - jesd22-a114-b v 8000 mttf 85 o c leadframe, 200 o c channel hours 1.2 x 10 6
xd010-14s-d4f 925-960 mhz 15w power amp module 303 s. technology court phone: (800) smi-mmic http://www.sirenza.com broomfield, co 80021 3 eds-102936 rev e gain and efficiency vs. output power and temperature freq=950 mhz edge, vdd=28 v 0 5 10 15 20 25 30 35 40 024681012 output power (w) gain (db), efficiency (%) gain @ -20c gain @25c gain @ 90c efficiency @ -20c efficiency @ 25c efficiency @ 90c typical performance curves evm and id vs. output power and temperature freq=950 mhz edge, vdd=28 v 0 1 2 3 4 5 6 024681012 output power (w) evm (%) 0.2 0.4 0.6 0.8 1 1.2 1.4 id (amps) evm @-20c evm @ 25c evm @ 90c id @ -20c id @ 25c id @ 90c gain and evm vs. output power and voltage freq=942 mhz edge, vdd=24v, 28v, 32v tflange= 25c 0 5 10 15 20 25 30 35 024681012 output power (w) gain (db), evm (%) gain @ 24 vdc gain @ 28 vdc gain @ 32 vdc evm @ 24 vdc evm @ 28 vdc evm @ 32 vdc gain, efficiency, evm vs. frequency output power= 8 w edge, vdd=28 v tflange=25c 0 5 10 15 20 25 30 35 920 930 940 950 960 970 frequency (mhz) gain (db), efficiency (%), evm (%) -35 -30 -25 -20 -15 -10 -5 0 input return loss (db ) gain efficiency evm input return loss
xd010-14s-d4f 925-960 mhz 15w power amp module 303 s. technology court phone: (800) smi-mmic http://www.sirenza.com broomfield, co 80021 4 eds-102936 rev e test board schematic with module connections shown test board layout to receive gerber files, dxf drawings, a detailed bom, and assem bly recommendations for the test board with fixture, contact ap plications support at support@sirenza.com. data sheet for evaluation circuit (xd010-eval) available from sirenza website. component description manufacturer pcb rogers 4350, e r = 3 . 5 thickness=30mils rogers j1, j2 sma, rf, panel mount tab w / flange johnson j3 mta post header, 6 pin, rect- angle, polarized, surface mount amp c1, c10 cap, 10 m f, 35v, 10%, tant, elect, d kemet c2, c20 cap, 0.1 m f, 100v, 10%, 1206 johanson c3, c30 cap, 1000pf, 100v, 10%, 1206 johanson c25, c26 cap, 68pf, 250v, 5%, 0603 atc c21, c22 cap, 0.1 m f, 100v, 10%, 0805 panasonic c23, c24 cap, 1000pf, 100v, 10%, 0603 avx mounting screws 4-40 x 0.250? various test board bill of materials
xd010-14s-d4f 925-960 mhz 15w power amp module 303 s. technology court phone: (800) smi-mmic http://www.sirenza.com broomfield, co 80021 5 eds-102936 rev e recommended pcb cutout and land ing pads for the d4f package note 3: dimensions are in inches refer to application note an-060 ?installation instructions fo r xd module series? for additional mounting info. app note ava ilbale at at www.sirenza.com package outline drawing
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